Study and characterization of GaN MOS capacitors: Planar vs trench topographies

Developing high quality GaN/dielectric interfaces is a fundamental step for manufacturing GaN vertical power transistors. In this paper, we quantitatively investigate the effect of planar etching treatment and trench formation on performance GaN-based MOS (metal oxide semiconductor) stacks. The results demonstrate that (i) blanket surface does not degrade robustness deposited dielectric layer; (ii) addition etch, while improving reproducibility, in decrease breakdown compared to structures. (iii) structures, voltage 10 years lifetime still above 20 V, indicating good robustness. (iv) To review trapping across metal-dielectric-GaN stack, forward-reverse capacitance-voltage measurements with without stress photo-assistance are performed. Overall, as-grown capacitors devoid prior steps show lowest trapping, have higher interface bulk comparable etched capacitors. (v) nanostructure was characterized by resolution scanning transmission electron microscopy (HR-STEM). An increased roughness 2-3 monolayers at observed after etching, which correlated density traps. presented paper give insight how etch processing affects trench-gate GaN-MOSFETs, provide guidance optimization device performance.